This invention relates to a high-speed serial interface, especially in a programmable logic device (PLD), which may operate at different data rates.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial input/output (I/O) standards. Many of these standards can operate at more than one clock rate. Moreover, under such standards, it is common not to send a separate clock signal with the data, but rather for the clock to be recovered from the data. In such cases, even after clock-data recovery (CDR) circuitry locks onto the recovered clock, it may be necessary to control clock-data skew by aligning the phase of the data and of the clock. However, there may be conditions under which the clock cannot be recovered or is outside the normal range of operation of the interface. These conditions are even more likely in a programmable logic device (PLD) where the particular application to which a user may put the device, and the interface, cannot be known at the time of manufacture.
In addition, such interfaces usually operate serially, but the device may operate internally in parallel, meaning that the interface must be able to convert between serial and parallel data, and to correct data word misalignment (i.e., errors in designating the bit boundaries between data words) during such conversions. And parallel different data on different lines may arrive at the receiver at different times, so that not all data that belong together are captured in the same clock cycle.
Moreover, these conditions arise more frequently as data rates continue to increase to 1.25 Gbps and above. As data rates exceed 1 Gbps, the window of time for sampling the data becomes smaller, resulting in increased jitter. Board skew and supply variations (e.g., due to temperature) become more significant as unit intervals become smaller than 1 ns.
System designers—particularly designers of systems for programmable logic devices—must keep all of these issues in mind in their designs to maintain signal accuracy and integrity. Some of the techniques that designers must rely on include constraints on integrated circuit and printed circuit board materials, and provision of extra components to reduce the occurrence and/or effects supply and temperature fluctuations.
It would be desirable to be able to provide, in a high-speed serial interface, particularly in a PLD, that can handle a wide range of situations that might affect clock and data accuracy and integrity.